1. Field of the Invention
The invention is directed to a method for manufacturing complementary MOS field effect transistors that is useful in the micron and submicron technology and more particularly to use of a P+ ion implantation to form the P channel devices using a maskless technique.
2. Description of the Prior Art
The complimentary MOS field effect transistor process has more steps to complete than either the N channel or P channel process. With this greater complexity, there is clearly a yield loss. The complexity comes with additional masks.
The conventional complimentary MOS field effect transistor process uses two block out masks. One of these masks is used to block out the designated P channel regions from unwanted ion implantation during the N channel ion implantation steps. The second mask is used to block out the designated N channel regions from unwanted ion implantation during the P channel ion implantation steps. The details of this conventional process can be generally seen from the H. J. Levinstein et al. U.S. Pat. No. 4,555,842 and W. Mueller, U.S. Pat. No. 4,760,033.
Workers in the field have tried to reduce these number of steps. One attempt is described in the "VLSI Technology" Second Edition by S. M. Sze Published by McGraw-Hill International Editions, 1988 on pages 485, 486 wherein a single block out mask is used. The described process provides the silicon substrate with N wells and P wells, and gate dielectric/gate electrode structures over the designated channel regions for the N channel and P channel devices. The P type impurity, boron is implanted nonselectively into all the sources and drains. This is followed with a selective, that is using a block out mask over designated P channel regions, implant of phosphorus or arsenic into the N channel source/drain regions at a higher dose, so that it overcompensates the boron. After the subsequent thermal cycles, the phosphorus or arsenic completely covers the boron vertically and laterally. Nevertheless, the unwanted boron ions do exist in the N channel regions when this method is used.
It is therefore a principal object of this invention to describe a process that uses only one block out mask to form a complementary MOS field effect transistor while keeping the unwanted P type ions in the N channel source/drain regions to a bare minimum.